We see a similar pattern, but interestingly enough, it’s not the same. I was supposed to work on getting the SiI up and running , but UPS delivered a nice package today:. And at the end you have a suffix with 2 slow clock cycles. My money is on the clock speed: While the Terasic was rock solid in its communication with the Color3 board. In addition, there are roughly 3 idle cycles between a fast clock group. When you zoom in on the slow clock cycles, you can measure a TCK frequency of kHz:
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Terasic vs Cheap Clone USB Blaster
If we ignore for a second that the cheap clone doesn’t work altsra this particular board, the biggest consequence of the chapeau clone is that bulk transfers are much slower: Meanwhile, during a fast clock group, the clock toggles at 6MHz.
In addition, there are roughly 3 idle cycles between a fast clock group. The Terasic doesn’t have that problem: This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command.
And here’s the equivalent of the cheap clone.
Altera USB Blaster Driver Installation Instructions
The most important signal here is TCK, in yellow. But the cheap clone runs TCK at exactly double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable. And at the end you have a suffix with 2 slow clock cycles. We see a similar pattern, but interestingly enough, it’s not the same. It’s not that it’s broken: In the middle we have the expected 16 fast clock groups.
A fast clock group sets the clock at tearsic instead of 6MHz.
There are 3 major sections: About Us Contact Hackaday. All processing is done with a simply state machine.
While the Terasic was rock solid in terqsic communication with the Color3 board. As I wrote earlierthe biggest issue with the cheap clone is that it doesn’t work on my eeColor Color3 board.
A really interesting difference is in the spacing between fast clock groups: What remains is the question about why the cheap clone doesn’t work. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today: For the cheap clone, the spacing is huge: Zooming in on the slow clocks, we see a clock frequency of kHz.
It looks like the cheap clone is able to squeeze out bits really fast, blasyer there’s quite a bit of software overhead in processing the next byte in the USB packet.
We have a prefix with 8 slow clocks, but in between the second and the third slow clock, there’s a signal fast clock group.
For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan DR or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of a scan data register. The cheap clone was never able to get reliable contact. For the overview, look at the upper set. When you zoom in on the slow clock cycles, you can measure a TCK frequency of kHz: It may be that 12MHz is really just pushing things too much.
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My money is on the clock speed: I was supposed to work on getting the SiI teraasic and runningbut UPS delivered a nice package today:. The suffix is really different, with 6 clock clocks but also a fast clock group in between.
Sign up Already a member? The set of signals below that is a slightly zoomed in version of the one above.